1. Field of the Invention
The present invention relates generally to digital circuits and specifically to a comparator circuit.
2. Background of the Prior Art
Greater/smaller or equal comparisons between n-bits of two data strings or input vectors are a staple operation of processors. A comparator performs these comparison operations on the primary bits of the two data or input vectors and generates some form of information depending on the values of the vectors. This information is then passed along to merging stages. These stages take the information from pairs of bits, merge it again into the same information and pass it along. The next level of merge units receive the information on pairs of pairs and merge that again. At each stage, the information at the output of a merge unit relates to two times the bits of the one earlier stage.
In most prior art comparators in processors, the vectors are inputted to AND gates and the outputs of the AND gates are inputted to a NOR logic gate which merges the information. The AND gates pass along information in the form of the following two signals: if the two vectors up to that point are equal; or if one is greater than the other. The NOR logic gate generates a &gt;= signal. For instance, an output signal is high if n-bit vector A is greater or equal to n-bit vector B. Further, in the classical case a comparator requires an additional logic stage having an INV gate. Therefore, in the classical comparator the merge units are actually three simple logic stages NAND-INV-NOR or NOR-INV-NAND. A NOR circuit includes stacked-p transistors which are inherently slower than non-stacked-p devices. Still further, the classical comparator, with its = and &gt; tree structure is inherently redundant and not fully testable. Generally, the process of generating and carrying forward A=B A&gt;B signals involves more circuitry and is slower in speed as compared to generating and carrying A&gt;=B and B&gt;=A signals.